1. Field of the Invention
The present invention relates to a semiconductor device having a trench gate and a manufacture method therefor.
Priority is claimed on Japanese Patent Application No. 2006-318726 filed on Nov. 27, 2006, the contents of which are incorporated herein by reference.
2. Description of the Related Art
Each memory cell in a DRAM (Dynamic Random Access Memory) or the like includes a selection transistor and a capacitor. The microfabrication of semiconductor elements leads to size reduction of MOS (Metal Oxide Semiconductor) transistors, which makes the short channel effect of MOS transistors prominent. In a large-capacity DRAM, the size reduction of the memory cells makes the channel length of transfer gate transistors shorter, thus reducing the performance of the transfer gate transistors. This brings about problems of impairing the retention and writing characteristics of the DRAM memory cells. In the following description, the “transfer gate transistor” is described as “memory cell transistor”.
As one way of dealing with the short channel of transistors, trench gate transistors having a channel with a three-dimensional structure have been developed. This trench gate transistor has a trench formed in a semiconductor substrate and makes the channel length longer by effectively using a three-dimensional trench interface as a channel. One example of the configuration of a DRAM using such a trench gate transistor (also called as RCAT (Recess Channel Access Transistor)) will be described below referring to FIGS. 15 and 16. FIG. 15 is a conceptual diagram showing the planar structure of a memory cell, and FIG. 16 is a conceptual diagram of the cross section of the memory cell along line A-A′ shown in FIG. 15.
A memory cell section 101 shown in FIG. 15 is one example of a structure where 2-bit memory cells are laid out in a single active region.
The memory cell section 101 is roughly structured by arraying a plurality of elongated active regions 102, slightly skewed in a planar view in FIG. 15, in a corresponding area of a semiconductor substrate, at predetermined intervals in a horizontal (X) direction and a vertical (Y) direction, providing a bit line contact (not shown) at a center portion of each active region 102, and providing a memory cell transistor (not shown) and a capacitor (not shown) connected to a substrate contact 105 on both right and left sides of the bit line contact. In the illustrated structure, multiple memory cells are repeatedly laid out in a matrix form with a plurality of serpentine bit lines 106, laid out in the horizontal (X) direction, and a plurality of word lines (including gate electrodes) 107, laid out in the vertical (Y) direction, as common interconnection lines. A selective epitaxial layer 103 is formed on those surface regions of the semiconductor substrate which become a source and a drain, and LDD (Lightly Doped Drain) side walls 108 are formed on side walls of the word line 107.
The cross-sectional structure of the memory cell section shown in FIG. 16 has a trench isolation dielectric film 110, a trench 111, a gate oxide film 112, a gate electrode 113, a first conductive layer 114 provided inside a substrate contact, a lightly doped impurity diffusion layer 115, a heavily doped impurity diffusion layer 116, a dielectric layer mask 117 provided on a gate electrode, a second conductive layer 119 provided in the substrate contact, an oxide film 120 provided on side walls of the gate electrode, and the LDD side walls 108.
The following patent document is known as a prior art document relating to such a trench gate transistor.
Japanese Unexamined Patent Application, First Publication No. H6-13621 discloses the structure of a trench gate MOS-FET (Field Effect Transistor) where to improve the breakdown voltage by relaxing the concentration of an electric field at that portion of an N-drift layer 2 which lies near a gate electrode 5, a first gate dielectric film 6a, located between the gate electrode 5 and the N-drift layer 2, is made thinner than a second gate dielectric film 6b, located between the gate electrode 5 and that portion of a well region 3 where a channel is to be formed, so that when a reverse bias is applied to the gate electrode 5, the conductivity type of the portion of the N-drift layer 2 which lies near the gate electrode 5 is inverted to a P type.
While the trench gate transistor with the structure typified by the one shown in FIGS. 15 and 16 is advantageous over a planar transistor in that the gate length can be made longer at shorter gate pitches, it has a problem of having a large gate capacitance.
In a planar transistor, gate electrodes are positioned only on a semiconductor substrate and the side of a gate electrode that faces diffusion layers where a source and a drain are to be formed is limited to a two-dimensionally overlapping region at the surface of the semiconductor substrate. In a transistor with a trench gate structure, by way of contrast, diffusion layers are in contact not only with the surface of the semiconductor substrate but also upper side walls in a trench, increasing the area of the overlapping region of the gate electrode and the diffusion layers. This increases the gate capacitance. The overlapping region becomes a gate electrode or a parasitic capacitor of a word line in the DRAM, and therefore causes an operational delay, which impedes a fast operation.
It is therefore desirable that the conventional trench gate transistor should have such a structure as to be able to reduce the gate capacitance.
For example, while a DRAM having a trench gate transistor which can ensure microfabrication of the circuit of the memory cell section by reducing the gate length has an advantage of improving the refresh characteristics, the DRAM faces the problem of an increase in power consumption caused as the value of the current needed to write data increases due to the increased gate capacitance.